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ad_2_uart
Commit 58fc9750 authored by JiangYixing's avatar JiangYixing
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update vol

parent 428cb4ca
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Showing with 4709 additions and 4602 deletions
fpga_prj.cache/wt/project.wpc
View file @ 58fc9750
version:1
57656254616c6b5472616e736d697373696f6e417474656d70746564:35
6d6f64655f636f756e7465727c4755494d6f6465:35
6d6f64655f636f756e7465727c4755494d6f6465:36
eof:
fpga_prj.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wcfg
View file @ 58fc9750
......@@ -10,11 +10,11 @@
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0"></ZoomStartTime>
<ZoomEndTime time="4,096"></ZoomEndTime>
<Cursor1Time time="0"></Cursor1Time>
<ZoomEndTime time="4,097"></ZoomEndTime>
<Cursor1Time time="801"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="83"></NameColumnWidth>
<NameColumnWidth column_width="79"></NameColumnWidth>
<ValueColumnWidth column_width="58"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="3" />
......
fpga_prj.runs/.jobs/vrs_config_56.xml 0 → 100644
View file @ 58fc9750
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
fpga_prj.runs/.jobs/vrs_config_57.xml 0 → 100644
View file @ 58fc9750
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
fpga_prj.runs/.jobs/vrs_config_58.xml 0 → 100644
View file @ 58fc9750
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
fpga_prj.runs/.jobs/vrs_config_59.xml 0 → 100644
View file @ 58fc9750
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
fpga_prj.runs/.jobs/vrs_config_60.xml 0 → 100644
View file @ 58fc9750
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
fpga_prj.runs/.jobs/vrs_config_61.xml 0 → 100644
View file @ 58fc9750
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
fpga_prj.runs/.jobs/vrs_config_62.xml 0 → 100644
View file @ 58fc9750
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="fifo_generator_0_synth_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/fifo_generator_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
fpga_prj.runs/.jobs/vrs_config_63.xml 0 → 100644
View file @ 58fc9750
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="fifo_generator_0_synth_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/fifo_generator_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="synth_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado">
<Parent Id="fifo_generator_0_synth_1"/>
</Run>
<Run Id="impl_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
<Parent Id="fifo_generator_0_synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
fpga_prj.runs/.jobs/vrs_config_64.xml 0 → 100644
View file @ 58fc9750
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="ila_0_synth_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/ila_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
fpga_prj.runs/.jobs/vrs_config_65.xml 0 → 100644
View file @ 58fc9750
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="ila_0_synth_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/ila_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="synth_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado">
<Parent Id="ila_0_synth_1"/>
</Run>
<Run Id="impl_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
<Parent Id="ila_0_synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
fpga_prj.runs/.jobs/vrs_config_66.xml 0 → 100644
View file @ 58fc9750
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
fpga_prj.runs/.jobs/vrs_config_67.xml 0 → 100644
View file @ 58fc9750
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
fpga_prj.runs/.jobs/vrs_config_68.xml 0 → 100644
View file @ 58fc9750
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
fpga_prj.runs/fifo_generator_0_synth_1/.vivado.begin.rst
View file @ 58fc9750
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="28568" HostCore="16" HostMemory="017109299200">
<Process Command="vivado.bat" Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="29140" HostCore="16" HostMemory="017109299200">
</Process>
</ProcessHandle>
fpga_prj.runs/fifo_generator_0_synth_1/dont_touch.xdc
View file @ 58fc9750
# This file is automatically generated.
# It contains project source information necessary for synthesis and implementation.
# IP: e:/verilogcode/AD_2_UART_V8/fpga_prj.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0.xci
# IP: E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0.xci
# IP: The module: 'fifo_generator_0' is the root of the design. Do not add the DONT_TOUCH constraint.
# XDC: e:/verilogcode/AD_2_UART_V8/fpga_prj.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc
# XDC: e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc
# XDC: The top module name and the constraint reference have the same name: 'fifo_generator_0'. Do not add the DONT_TOUCH constraint.
set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
# XDC: e:/verilogcode/AD_2_UART_V8/fpga_prj.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc
# XDC: e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc
# XDC: The top module name and the constraint reference have the same name: 'fifo_generator_0'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
# XDC: e:/verilogcode/AD_2_UART_V8/fpga_prj.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_ooc.xdc
# XDC: e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_ooc.xdc
# XDC: The top module name and the constraint reference have the same name: 'fifo_generator_0'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
# IP: e:/verilogcode/AD_2_UART_V8/fpga_prj.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0.xci
# IP: E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0.xci
# IP: The module: 'fifo_generator_0' is the root of the design. Do not add the DONT_TOUCH constraint.
# XDC: e:/verilogcode/AD_2_UART_V8/fpga_prj.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc
# XDC: e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc
# XDC: The top module name and the constraint reference have the same name: 'fifo_generator_0'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
# XDC: e:/verilogcode/AD_2_UART_V8/fpga_prj.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc
# XDC: e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc
# XDC: The top module name and the constraint reference have the same name: 'fifo_generator_0'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
# XDC: e:/verilogcode/AD_2_UART_V8/fpga_prj.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_ooc.xdc
# XDC: e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_ooc.xdc
# XDC: The top module name and the constraint reference have the same name: 'fifo_generator_0'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
fpga_prj.runs/fifo_generator_0_synth_1/fifo_generator_0_utilization_synth.rpt
View file @ 58fc9750
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
| Date : Thu Oct 12 10:38:15 2023
| Date : Sat Oct 14 09:20:39 2023
| Host : DESKTOP-NQ0GI1S running 64-bit major release (build 9200)
| Command : report_utilization -file fifo_generator_0_utilization_synth.rpt -pb fifo_generator_0_utilization_synth.pb
| Design : fifo_generator_0
......@@ -31,13 +31,13 @@ Table of Contents
+----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+------+-------+------------+-----------+-------+
| Slice LUTs* | 98 | 0 | 0 | 20800 | 0.47 |
| LUT as Logic | 96 | 0 | 0 | 20800 | 0.46 |
| Slice LUTs* | 88 | 0 | 0 | 20800 | 0.42 |
| LUT as Logic | 86 | 0 | 0 | 20800 | 0.41 |
| LUT as Memory | 2 | 0 | 0 | 9600 | 0.02 |
| LUT as Distributed RAM | 0 | 0 | | | |
| LUT as Shift Register | 2 | 0 | | | |
| Slice Registers | 190 | 0 | 0 | 41600 | 0.46 |
| Register as Flip Flop | 190 | 0 | 0 | 41600 | 0.46 |
| Slice Registers | 203 | 0 | 0 | 41600 | 0.49 |
| Register as Flip Flop | 203 | 0 | 0 | 41600 | 0.49 |
| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 16300 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 8150 | 0.00 |
......@@ -61,7 +61,7 @@ Warning! LUT value is adjusted to account for LUT combining.
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 8 | Yes | Set | - |
| 182 | Yes | Reset | - |
| 195 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
......@@ -71,9 +71,9 @@ Warning! LUT value is adjusted to account for LUT combining.
+-------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 1 | 0 | 0 | 50 | 2.00 |
| RAMB36/FIFO* | 1 | 0 | 0 | 50 | 2.00 |
| RAMB36E1 only | 1 | | | | |
| Block RAM Tile | 2 | 0 | 0 | 50 | 4.00 |
| RAMB36/FIFO* | 2 | 0 | 0 | 50 | 4.00 |
| RAMB36E1 only | 2 | | | | |
| RAMB18 | 0 | 0 | 0 | 100 | 0.00 |
+-------------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
......@@ -154,17 +154,17 @@ Warning! LUT value is adjusted to account for LUT combining.
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 182 | Flop & Latch |
| LUT2 | 38 | LUT |
| FDRE | 195 | Flop & Latch |
| LUT2 | 34 | LUT |
| LUT4 | 31 | LUT |
| LUT1 | 15 | LUT |
| LUT6 | 11 | LUT |
| LUT3 | 10 | LUT |
| LUT5 | 9 | LUT |
| CARRY4 | 14 | CarryLogic |
| FDSE | 8 | Flop & Latch |
| CARRY4 | 8 | CarryLogic |
| LUT3 | 6 | LUT |
| LUT6 | 5 | LUT |
| LUT5 | 5 | LUT |
| SRL16E | 2 | Distributed Memory |
| RAMB36E1 | 1 | Block Memory |
| RAMB36E1 | 2 | Block Memory |
+----------+------+---------------------+
......
fpga_prj.runs/fifo_generator_0_synth_1/gen_run.xml
View file @ 58fc9750
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="fifo_generator_0_synth_1" LaunchPart="xc7a35tfgg484-2" LaunchTime="1697078208">
<GenRun Id="fifo_generator_0_synth_1" LaunchPart="xc7a35tfgg484-2" LaunchTime="1697246349">
<File Type="PA-TCL" Name="fifo_generator_0.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="fifo_generator_0_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="fifo_generator_0_reports.tcl"/>
<File Type="RDS-RDS" Name="fifo_generator_0.vds"/>
<File Type="RDS-UTIL" Name="fifo_generator_0_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="fifo_generator_0_utilization_synth.pb"/>
<File Type="RDS-DCP" Name="fifo_generator_0.dcp"/>
<File Type="VDS-TIMINGSUMMARY" Name="fifo_generator_0_timing_summary_synth.rpt"/>
<File Type="VDS-TIMING-PB" Name="fifo_generator_0_timing_summary_synth.pb"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_generator_0" RelGenDir="$PGENDIR/fifo_generator_0">
<File Path="$PSRCDIR/sources_1/ip/fifo_generator_0/fifo_generator_0.xci">
<FileInfo>
......
fpga_prj.runs/fifo_generator_0_synth_1/project.wdf
View file @ 58fc9750
version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:35:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3130:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
......@@ -23,12 +23,12 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3138:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3138:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3138:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3230:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3230:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3230:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3137:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3138:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3138:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3138:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3230:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3230:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3230:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6137663738393234306465663438373238303030646163316164616538626431:506172656e742050412070726f6a656374204944:00
eof:1623812543
eof:480420555
fpga_prj.runs/fifo_generator_0_synth_1/runme.sh
View file @ 58fc9750
......@@ -25,7 +25,7 @@ else
fi
export LD_LIBRARY_PATH
HD_PWD='E:/verilogcode/AD_2_UART_V8/fpga_prj.runs/fifo_generator_0_synth_1'
HD_PWD='E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/fifo_generator_0_synth_1'
cd "$HD_PWD"
HD_LOG=runme.log
......
fpga_prj.runs/fifo_generator_0_synth_1/vivado.jou
View file @ 58fc9750
......@@ -3,12 +3,12 @@
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
# Start of session at: Thu Oct 12 10:36:53 2023
# Process ID: 22628
# Current directory: E:/verilogcode/AD_2_UART_V8/fpga_prj.runs/fifo_generator_0_synth_1
# Start of session at: Sat Oct 14 09:19:14 2023
# Process ID: 22112
# Current directory: E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/fifo_generator_0_synth_1
# Command line: vivado.exe -log fifo_generator_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo_generator_0.tcl
# Log file: E:/verilogcode/AD_2_UART_V8/fpga_prj.runs/fifo_generator_0_synth_1/fifo_generator_0.vds
# Journal file: E:/verilogcode/AD_2_UART_V8/fpga_prj.runs/fifo_generator_0_synth_1\vivado.jou
# Log file: E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/fifo_generator_0_synth_1/fifo_generator_0.vds
# Journal file: E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/fifo_generator_0_synth_1\vivado.jou
# Running On: DESKTOP-NQ0GI1S, OS: Windows, CPU Frequency: 3394 MHz, CPU Physical cores: 16, Host memory: 17109 MB
#-----------------------------------------------------------
source fifo_generator_0.tcl -notrace
fpga_prj.runs/ila_0_synth_1/.vivado.begin.rst
View file @ 58fc9750
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="14148" HostCore="16" HostMemory="017109299200">
<Process Command="vivado.bat" Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="21716" HostCore="16" HostMemory="017109299200">
</Process>
</ProcessHandle>
fpga_prj.runs/ila_0_synth_1/dont_touch.xdc
View file @ 58fc9750
# This file is automatically generated.
# It contains project source information necessary for synthesis and implementation.
# IP: E:/verilogcode/AD_2_UART_V8/fpga_prj.srcs/sources_1/ip/ila_0/ila_0.xci
# IP: E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.srcs/sources_1/ip/ila_0/ila_0.xci
# IP: The module: 'ila_0' is the root of the design. Do not add the DONT_TOUCH constraint.
# XDC: e:/verilogcode/AD_2_UART_V8/fpga_prj.gen/sources_1/ip/ila_0/ila_v6_2/constraints/ila_impl.xdc
# XDC: e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/ila_0/ila_v6_2/constraints/ila_impl.xdc
# XDC: The top module name and the constraint reference have the same name: 'ila_0'. Do not add the DONT_TOUCH constraint.
set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
# XDC: e:/verilogcode/AD_2_UART_V8/fpga_prj.gen/sources_1/ip/ila_0/ila_v6_2/constraints/ila.xdc
# XDC: e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/ila_0/ila_v6_2/constraints/ila.xdc
# XDC: The top module name and the constraint reference have the same name: 'ila_0'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
# XDC: e:/verilogcode/AD_2_UART_V8/fpga_prj.gen/sources_1/ip/ila_0/ila_0_ooc.xdc
# XDC: e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/ila_0/ila_0_ooc.xdc
# XDC: The top module name and the constraint reference have the same name: 'ila_0'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
# IP: E:/verilogcode/AD_2_UART_V8/fpga_prj.srcs/sources_1/ip/ila_0/ila_0.xci
# IP: E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.srcs/sources_1/ip/ila_0/ila_0.xci
# IP: The module: 'ila_0' is the root of the design. Do not add the DONT_TOUCH constraint.
# XDC: e:/verilogcode/AD_2_UART_V8/fpga_prj.gen/sources_1/ip/ila_0/ila_v6_2/constraints/ila_impl.xdc
# XDC: e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/ila_0/ila_v6_2/constraints/ila_impl.xdc
# XDC: The top module name and the constraint reference have the same name: 'ila_0'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
# XDC: e:/verilogcode/AD_2_UART_V8/fpga_prj.gen/sources_1/ip/ila_0/ila_v6_2/constraints/ila.xdc
# XDC: e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/ila_0/ila_v6_2/constraints/ila.xdc
# XDC: The top module name and the constraint reference have the same name: 'ila_0'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
# XDC: e:/verilogcode/AD_2_UART_V8/fpga_prj.gen/sources_1/ip/ila_0/ila_0_ooc.xdc
# XDC: e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/ila_0/ila_0_ooc.xdc
# XDC: The top module name and the constraint reference have the same name: 'ila_0'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
fpga_prj.runs/ila_0_synth_1/gen_run.xml
View file @ 58fc9750
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ila_0_synth_1" LaunchPart="xc7a35tfgg484-2" LaunchTime="1697078302">
<GenRun Id="ila_0_synth_1" LaunchPart="xc7a35tfgg484-2" LaunchTime="1697246830">
<File Type="PA-TCL" Name="ila_0.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="ila_0_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="ila_0_reports.tcl"/>
<File Type="RDS-RDS" Name="ila_0.vds"/>
<File Type="RDS-UTIL" Name="ila_0_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="ila_0_utilization_synth.pb"/>
<File Type="RDS-DCP" Name="ila_0.dcp"/>
<File Type="VDS-TIMINGSUMMARY" Name="ila_0_timing_summary_synth.rpt"/>
<File Type="VDS-TIMING-PB" Name="ila_0_timing_summary_synth.pb"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_0" RelGenDir="$PGENDIR/ila_0">
<File Path="$PSRCDIR/sources_1/ip/ila_0/ila_0.xci">
<FileInfo>
......
fpga_prj.runs/ila_0_synth_1/ila_0.tcl
View file @ 58fc9750
This diff is collapsed.
fpga_prj.runs/ila_0_synth_1/ila_0.vds
View file @ 58fc9750
This diff is collapsed.
fpga_prj.runs/ila_0_synth_1/ila_0_utilization_synth.rpt
View file @ 58fc9750
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
| Date : Thu Oct 12 10:40:42 2023
| Date : Sat Oct 14 09:29:33 2023
| Host : DESKTOP-NQ0GI1S running 64-bit major release (build 9200)
| Command : report_utilization -file ila_0_utilization_synth.rpt -pb ila_0_utilization_synth.pb
| Design : ila_0
......@@ -31,13 +31,13 @@ Table of Contents
+----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+------+-------+------------+-----------+-------+
| Slice LUTs* | 789 | 0 | 0 | 20800 | 3.79 |
| LUT as Logic | 670 | 0 | 0 | 20800 | 3.22 |
| LUT as Memory | 119 | 0 | 0 | 9600 | 1.24 |
| Slice LUTs* | 785 | 0 | 0 | 20800 | 3.77 |
| LUT as Logic | 664 | 0 | 0 | 20800 | 3.19 |
| LUT as Memory | 121 | 0 | 0 | 9600 | 1.26 |
| LUT as Distributed RAM | 0 | 0 | | | |
| LUT as Shift Register | 119 | 0 | | | |
| Slice Registers | 1356 | 0 | 0 | 41600 | 3.26 |
| Register as Flip Flop | 1356 | 0 | 0 | 41600 | 3.26 |
| LUT as Shift Register | 121 | 0 | | | |
| Slice Registers | 1362 | 0 | 0 | 41600 | 3.27 |
| Register as Flip Flop | 1362 | 0 | 0 | 41600 | 3.27 |
| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 |
| F7 Muxes | 19 | 0 | 0 | 16300 | 0.12 |
| F8 Muxes | 0 | 0 | 0 | 8150 | 0.00 |
......@@ -61,7 +61,7 @@ Warning! LUT value is adjusted to account for LUT combining.
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 10 | Yes | Set | - |
| 1346 | Yes | Reset | - |
| 1352 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
......@@ -154,14 +154,14 @@ Warning! LUT value is adjusted to account for LUT combining.
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 1346 | Flop & Latch |
| LUT6 | 356 | LUT |
| LUT5 | 147 | LUT |
| LUT4 | 97 | LUT |
| SRL16E | 93 | Distributed Memory |
| LUT3 | 77 | LUT |
| FDRE | 1352 | Flop & Latch |
| LUT6 | 376 | LUT |
| LUT5 | 110 | LUT |
| LUT4 | 98 | LUT |
| SRL16E | 95 | Distributed Memory |
| LUT3 | 78 | LUT |
| SRLC32E | 64 | Distributed Memory |
| LUT2 | 33 | LUT |
| LUT2 | 51 | LUT |
| LUT1 | 29 | LUT |
| CARRY4 | 26 | CarryLogic |
| MUXF7 | 19 | MuxFx |
......
fpga_prj.runs/ila_0_synth_1/project.wdf
View file @ 58fc9750
version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:35:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3130:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
......@@ -23,12 +23,12 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3139:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3139:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3139:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3231:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3231:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3231:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3137:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3139:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3139:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3139:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3231:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3231:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3231:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6137663738393234306465663438373238303030646163316164616538626431:506172656e742050412070726f6a656374204944:00
eof:2262780251
eof:4206133807
fpga_prj.runs/ila_0_synth_1/runme.log
View file @ 58fc9750
This diff is collapsed.
fpga_prj.runs/ila_0_synth_1/runme.sh
View file @ 58fc9750
......@@ -25,7 +25,7 @@ else
fi
export LD_LIBRARY_PATH
HD_PWD='E:/verilogcode/AD_2_UART_V8/fpga_prj.runs/ila_0_synth_1'
HD_PWD='E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/ila_0_synth_1'
cd "$HD_PWD"
HD_LOG=runme.log
......
fpga_prj.runs/ila_0_synth_1/vivado.jou
View file @ 58fc9750
......@@ -3,12 +3,12 @@
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
# Start of session at: Thu Oct 12 10:38:27 2023
# Process ID: 28140
# Current directory: E:/verilogcode/AD_2_UART_V8/fpga_prj.runs/ila_0_synth_1
# Start of session at: Sat Oct 14 09:27:14 2023
# Process ID: 24500
# Current directory: E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/ila_0_synth_1
# Command line: vivado.exe -log ila_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_0.tcl
# Log file: E:/verilogcode/AD_2_UART_V8/fpga_prj.runs/ila_0_synth_1/ila_0.vds
# Journal file: E:/verilogcode/AD_2_UART_V8/fpga_prj.runs/ila_0_synth_1\vivado.jou
# Log file: E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/ila_0_synth_1/ila_0.vds
# Journal file: E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/ila_0_synth_1\vivado.jou
# Running On: DESKTOP-NQ0GI1S, OS: Windows, CPU Frequency: 3394 MHz, CPU Physical cores: 16, Host memory: 17109 MB
#-----------------------------------------------------------
source ila_0.tcl -notrace
fpga_prj.runs/impl_1/.init_design.begin.rst
View file @ 58fc9750
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="31276">
<Process Command=".planAhead." Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="12284">
</Process>
</ProcessHandle>
fpga_prj.runs/impl_1/.opt_design.begin.rst
View file @ 58fc9750
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="31276">
<Process Command=".planAhead." Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="12284">
</Process>
</ProcessHandle>
fpga_prj.runs/impl_1/.phys_opt_design.begin.rst
View file @ 58fc9750
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="31276">
<Process Command=".planAhead." Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="12284">
</Process>
</ProcessHandle>
fpga_prj.runs/impl_1/.place_design.begin.rst
View file @ 58fc9750
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="31276">
<Process Command=".planAhead." Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="12284">
</Process>
</ProcessHandle>
fpga_prj.runs/impl_1/.route_design.begin.rst
View file @ 58fc9750
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="31276">
<Process Command=".planAhead." Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="12284">
</Process>
</ProcessHandle>
fpga_prj.runs/impl_1/.vivado.begin.rst
View file @ 58fc9750
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="7056" HostCore="16" HostMemory="017109299200">
<Process Command="vivado.bat" Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="30892" HostCore="16" HostMemory="017109299200">
</Process>
</ProcessHandle>
fpga_prj.runs/impl_1/.write_bitstream.begin.rst
View file @ 58fc9750
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="31276">
<Process Command=".planAhead." Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="12284">
</Process>
</ProcessHandle>
fpga_prj.runs/impl_1/ad7606_top.ltx
View file @ 58fc9750
......@@ -237,6 +237,38 @@
]
}
]
},
{
"name": "probe4",
"id": 4,
"type": "DATA",
"direction": "IN",
"isVector": false,
"leftIndex": 0,
"rightIndex": 0,
"portIndex": 4,
"nets": [
{
"name": "empty",
"isBus": false
}
]
},
{
"name": "probe5",
"id": 5,
"type": "DATA",
"direction": "IN",
"isVector": false,
"leftIndex": 0,
"rightIndex": 0,
"portIndex": 5,
"nets": [
{
"name": "full",
"isBus": false
}
]
}
]
}
......
fpga_prj.runs/impl_1/ad7606_top.tcl
View file @ 58fc9750
......@@ -17,7 +17,7 @@ proc create_report { reportName command } {
}
}
namespace eval ::optrace {
variable script "E:/verilogcode/AD_2_UART_V10/fpga_prj.runs/impl_1/ad7606_top.tcl"
variable script "E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1/ad7606_top.tcl"
variable category "vivado_impl"
}
......@@ -122,7 +122,9 @@ start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
set_param tcl.collectionResultDisplayLimit 0
set_param chipscope.maxJobs 4
set_param xicom.use_bs_reader 1
set_param runs.launchOptions { -jobs 8 }
OPTRACE "create in-memory project" START { }
create_project -in_memory -part xc7a35tfgg484-2
......@@ -130,19 +132,19 @@ OPTRACE "create in-memory project" START { }
set_param project.singleFileAddWarning.threshold 0
OPTRACE "create in-memory project" END { }
OPTRACE "set parameters" START { }
set_property webtalk.parent_dir E:/verilogcode/AD_2_UART_V10/fpga_prj.cache/wt [current_project]
set_property parent.project_path E:/verilogcode/AD_2_UART_V10/fpga_prj.xpr [current_project]
set_property ip_output_repo E:/verilogcode/AD_2_UART_V10/fpga_prj.cache/ip [current_project]
set_property webtalk.parent_dir E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.cache/wt [current_project]
set_property parent.project_path E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.xpr [current_project]
set_property ip_output_repo E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
OPTRACE "set parameters" END { }
OPTRACE "add files" START { }
add_files -quiet E:/verilogcode/AD_2_UART_V10/fpga_prj.runs/synth_1/ad7606_top.dcp
read_ip -quiet E:/verilogcode/AD_2_UART_V10/fpga_prj.srcs/sources_1/ip/ila_0/ila_0.xci
read_ip -quiet E:/verilogcode/AD_2_UART_V10/fpga_prj.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
read_ip -quiet E:/verilogcode/AD_2_UART_V10/fpga_prj.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0.xci
add_files -quiet E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/synth_1/ad7606_top.dcp
read_ip -quiet E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.srcs/sources_1/ip/ila_0/ila_0.xci
read_ip -quiet E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
read_ip -quiet E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0.xci
OPTRACE "read constraints: implementation" START { }
read_xdc E:/verilogcode/AD_2_UART_V10/uisrc/04_pin/fpga_pin.xdc
read_xdc E:/verilogcode/AD_2_UART_V10_vol/uisrc/04_pin/fpga_pin.xdc
OPTRACE "read constraints: implementation" END { }
OPTRACE "add files" END { }
OPTRACE "link_design" START { }
......
fpga_prj.runs/impl_1/ad7606_top.vdi
View file @ 58fc9750
This diff is collapsed.
fpga_prj.runs/impl_1/ad7606_top_drc_opted.rpt
View file @ 58fc9750
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
| Date : Fri Oct 13 10:16:15 2023
| Date : Sat Oct 14 09:52:51 2023
| Host : DESKTOP-NQ0GI1S running 64-bit major release (build 9200)
| Command : report_drc -file ad7606_top_drc_opted.rpt -pb ad7606_top_drc_opted.pb -rpx ad7606_top_drc_opted.rpx
| Design : ad7606_top
......
fpga_prj.runs/impl_1/ad7606_top_drc_routed.rpt
View file @ 58fc9750
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
| Date : Fri Oct 13 10:17:06 2023
| Date : Sat Oct 14 09:53:44 2023
| Host : DESKTOP-NQ0GI1S running 64-bit major release (build 9200)
| Command : report_drc -file ad7606_top_drc_routed.rpt -pb ad7606_top_drc_routed.pb -rpx ad7606_top_drc_routed.rpx
| Design : ad7606_top
......@@ -36,22 +36,22 @@ Table of Contents
-----------------
PDCN-1569#1 Warning
LUT equation term check
Used physical LUT pin 'A2' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I1) is not included in the LUT equation: 'O5=(A1*A3)+(A1*(~A3)*(~A5))+((~A1))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
Used physical LUT pin 'A2' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I1) is not included in the LUT equation: 'O5=(A5*A3)+(A5*(~A3)*(~A1))+((~A5))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
Related violations: <none>
PDCN-1569#2 Warning
LUT equation term check
Used physical LUT pin 'A3' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1/I0) is not included in the LUT equation: 'O6=(A6+~A6)*((A5))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
Used physical LUT pin 'A2' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1/I0) is not included in the LUT equation: 'O6=(A6+~A6)*((A3))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
Related violations: <none>
PDCN-1569#3 Warning
LUT equation term check
Used physical LUT pin 'A4' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I0) is not included in the LUT equation: 'O5=(A1*A3)+(A1*(~A3)*(~A5))+((~A1))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
Used physical LUT pin 'A4' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I0) is not included in the LUT equation: 'O5=(A5*A3)+(A5*(~A3)*(~A1))+((~A5))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
Related violations: <none>
RTSTAT-10#1 Warning
No routable loads
43 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1],
41 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1],
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i,
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0],
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0],
......@@ -60,13 +60,13 @@ dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TMS,
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0],
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0],
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0],
fifo_inst/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/ENA_dly_D,
fifo_inst/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/ENA_dly_D,
fifo_inst/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0],
fifo_inst/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0],
fifo_inst_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/ENA_dly_D,
fifo_inst_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/ENA_dly_D,
fifo_inst_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0],
fifo_inst_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0]
(the first 15 of 33 listed).
(the first 15 of 31 listed).
Related violations: <none>
fpga_prj.runs/impl_1/ad7606_top_io_placed.rpt
View file @ 58fc9750
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
| Date : Fri Oct 13 10:16:28 2023
| Date : Sat Oct 14 09:53:04 2023
| Host : DESKTOP-NQ0GI1S running 64-bit major release (build 9200)
| Command : report_io -file ad7606_top_io_placed.rpt
| Design : ad7606_top
......
fpga_prj.runs/impl_1/ad7606_top_power_routed.rpt
View file @ 58fc9750
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
| Date : Fri Oct 13 10:17:10 2023
| Date : Sat Oct 14 09:53:48 2023
| Host : DESKTOP-NQ0GI1S running 64-bit major release (build 9200)
| Command : report_power -file ad7606_top_power_routed.rpt -pb ad7606_top_power_summary_routed.pb -rpx ad7606_top_power_routed.rpx
| Design : ad7606_top
......@@ -30,10 +30,10 @@ Table of Contents
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 0.131 |
| Total On-Chip Power (W) | 0.132 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 0.059 |
| Dynamic (W) | 0.060 |
| Device Static (W) | 0.072 |
| Effective TJA (C/W) | 2.8 |
| Max Ambient (C) | 84.6 |
......@@ -52,22 +52,23 @@ Table of Contents
+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks | 0.001 | 3 | --- | --- |
| Slice Logic | 0.002 | 5196 | --- | --- |
| LUT as Logic | 0.002 | 1487 | 20800 | 7.15 |
| Register | <0.001 | 2731 | 41600 | 6.56 |
| LUT as Shift Register | <0.001 | 100 | 9600 | 1.04 |
| CARRY4 | <0.001 | 79 | 8150 | 0.97 |
| BUFG | <0.001 | 8 | 32 | 25.00 |
| Clocks | <0.001 | 3 | --- | --- |
| Slice Logic | 0.002 | 5266 | --- | --- |
| LUT as Logic | 0.002 | 1497 | 20800 | 7.20 |
| Register | <0.001 | 2754 | 41600 | 6.62 |
| LUT as Shift Register | <0.001 | 102 | 9600 | 1.06 |
| CARRY4 | <0.001 | 99 | 8150 | 1.21 |
| BUFG | <0.001 | 7 | 32 | 21.88 |
| LUT as Distributed RAM | <0.001 | 24 | 9600 | 0.25 |
| F7/F8 Muxes | <0.001 | 19 | 32600 | 0.06 |
| Others | 0.000 | 339 | --- | --- |
| Signals | 0.002 | 3806 | --- | --- |
| Block RAM | <0.001 | 8 | 50 | 16.00 |
| Others | 0.000 | 358 | --- | --- |
| Signals | 0.002 | 3897 | --- | --- |
| Block RAM | <0.001 | 10 | 50 | 20.00 |
| MMCM | 0.054 | 1 | 5 | 20.00 |
| DSPs | <0.001 | 1 | 90 | 1.11 |
| I/O | <0.001 | 11 | 250 | 4.40 |
| Static Power | 0.072 | | | |
| Total | 0.131 | | | |
| Total | 0.132 | | | |
+--------------------------+-----------+----------+-----------+-----------------+
......@@ -77,7 +78,7 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint | 1.000 | 0.015 | 0.005 | 0.010 | NA | Unspecified | NA |
| Vccint | 1.000 | 0.016 | 0.006 | 0.010 | NA | Unspecified | NA |
| Vccaux | 1.800 | 0.043 | 0.030 | 0.013 | NA | Unspecified | NA |
| Vcco33 | 3.300 | 0.001 | 0.000 | 0.001 | NA | Unspecified | NA |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
......@@ -146,13 +147,14 @@ Table of Contents
+--------------------------+-----------+
| Name | Power (W) |
+--------------------------+-----------+
| ad7606_top | 0.059 |
| bcd1_ist | 0.001 |
| ad7606_top | 0.060 |
| clk_7606_inst | 0.054 |
| inst | 0.054 |
| dbg_hub | 0.001 |
| inst | 0.001 |
| BSCANID.u_xsdbm_id | 0.001 |
| volt_cal_inst | 0.002 |
| bcd1_ist | 0.002 |
+--------------------------+-----------+
fpga_prj.runs/impl_1/ad7606_top_route_status.rpt
View file @ 58fc9750
Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 5218 :
# of nets not needing routing.......... : 1408 :
# of internally routed nets........ : 1349 :
# of nets with no loads............ : 59 :
# of routable nets..................... : 3810 :
# of fully routed nets............. : 3810 :
# of logical nets.......................... : 5364 :
# of nets not needing routing.......... : 1463 :
# of internally routed nets........ : 1406 :
# of nets with no loads............ : 57 :
# of routable nets..................... : 3901 :
# of fully routed nets............. : 3901 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :
fpga_prj.runs/impl_1/debug_nets.ltx
View file @ 58fc9750
......@@ -237,6 +237,38 @@
]
}
]
},
{
"name": "probe4",
"id": 4,
"type": "DATA",
"direction": "IN",
"isVector": false,
"leftIndex": 0,
"rightIndex": 0,
"portIndex": 4,
"nets": [
{
"name": "empty",
"isBus": false
}
]
},
{
"name": "probe5",
"id": 5,
"type": "DATA",
"direction": "IN",
"isVector": false,
"leftIndex": 0,
"rightIndex": 0,
"portIndex": 5,
"nets": [
{
"name": "full",
"isBus": false
}
]
}
]
}
......
fpga_prj.runs/impl_1/gen_run.xml
View file @ 58fc9750
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7a35tfgg484-2" LaunchTime="1697163223">
<GenRun Id="impl_1" LaunchPart="xc7a35tfgg484-2" LaunchTime="1697248211">
<File Type="ROUTE-PWR" Name="ad7606_top_power_routed.rpt"/>
<File Type="PA-TCL" Name="ad7606_top.tcl"/>
<File Type="ROUTE-PWR-SUM" Name="ad7606_top_power_summary_routed.pb"/>
......@@ -142,16 +142,15 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/uisrc/01_rtl/ad7606_top.v">
<File Path="$PPRDIR/../AD_2_UART_V7_test/volt_cal.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../AD_2_UART_V7_test/volt_cal.v">
<File Path="$PPRDIR/uisrc/01_rtl/ad7606_top.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
......
fpga_prj.runs/impl_1/project.wdf
View file @ 58fc9750
......@@ -23,12 +23,12 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3230:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3230:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3230:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3232:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3232:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3232:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3137:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3230:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3230:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3230:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3232:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3232:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3232:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6137663738393234306465663438373238303030646163316164616538626431:506172656e742050412070726f6a656374204944:00
eof:480420555
eof:201319746
fpga_prj.runs/impl_1/runme.log
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fpga_prj.runs/impl_1/runme.sh
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......@@ -25,7 +25,7 @@ else
fi
export LD_LIBRARY_PATH
HD_PWD='E:/verilogcode/AD_2_UART_V10/fpga_prj.runs/impl_1'
HD_PWD='E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1'
cd "$HD_PWD"
HD_LOG=runme.log
......
fpga_prj.runs/impl_1/vivado.jou
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......@@ -3,12 +3,12 @@
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
# Start of session at: Fri Oct 13 10:15:02 2023
# Process ID: 31276
# Current directory: E:/verilogcode/AD_2_UART_V10/fpga_prj.runs/impl_1
# Start of session at: Sat Oct 14 09:51:37 2023
# Process ID: 12284
# Current directory: E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1
# Command line: vivado.exe -log ad7606_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source ad7606_top.tcl -notrace
# Log file: E:/verilogcode/AD_2_UART_V10/fpga_prj.runs/impl_1/ad7606_top.vdi
# Journal file: E:/verilogcode/AD_2_UART_V10/fpga_prj.runs/impl_1\vivado.jou
# Log file: E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1/ad7606_top.vdi
# Journal file: E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1\vivado.jou
# Running On: DESKTOP-NQ0GI1S, OS: Windows, CPU Frequency: 3394 MHz, CPU Physical cores: 16, Host memory: 17109 MB
#-----------------------------------------------------------
source ad7606_top.tcl -notrace
fpga_prj.runs/impl_1/vivado_22284.backup.jou 0 → 100644
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#-----------------------------------------------------------
# Vivado v2023.1 (64-bit)
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
# Start of session at: Sat Oct 14 08:58:02 2023
# Process ID: 22284
# Current directory: E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1
# Command line: vivado.exe -log ad7606_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source ad7606_top.tcl -notrace
# Log file: E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1/ad7606_top.vdi
# Journal file: E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/impl_1\vivado.jou
# Running On: DESKTOP-NQ0GI1S, OS: Windows, CPU Frequency: 3394 MHz, CPU Physical cores: 16, Host memory: 17109 MB
#-----------------------------------------------------------
source ad7606_top.tcl -notrace
fpga_prj.runs/synth_1/.Xil/ad7606_top_propImpl.xdc
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set_property SRC_FILE_INFO {cfile:E:/verilogcode/AD_2_UART_V10/uisrc/04_pin/fpga_pin.xdc rfile:../../../uisrc/04_pin/fpga_pin.xdc id:1} [current_design]
set_property SRC_FILE_INFO {cfile:E:/verilogcode/AD_2_UART_V10_vol/uisrc/04_pin/fpga_pin.xdc rfile:../../../uisrc/04_pin/fpga_pin.xdc id:1} [current_design]
set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN V4 [get_ports sysclk_i]
set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design]
......
fpga_prj.runs/synth_1/.vivado.begin.rst
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<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="27552" HostCore="16" HostMemory="017109299200">
<Process Command="vivado.bat" Owner="jtext103" Host="DESKTOP-NQ0GI1S" Pid="30956" HostCore="16" HostMemory="017109299200">
</Process>
</ProcessHandle>
fpga_prj.runs/synth_1/ad7606_top.tcl
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......@@ -4,7 +4,7 @@
set TIME_start [clock seconds]
namespace eval ::optrace {
variable script "E:/verilogcode/AD_2_UART_V10/fpga_prj.runs/synth_1/ad7606_top.tcl"
variable script "E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.runs/synth_1/ad7606_top.tcl"
variable category "vivado_synth"
}
......@@ -70,6 +70,9 @@ proc create_report { reportName command } {
}
}
OPTRACE "synth_1" START { ROLLUP_AUTO }
set_param tcl.collectionResultDisplayLimit 0
set_param chipscope.maxJobs 4
set_param xicom.use_bs_reader 1
OPTRACE "Creating in-memory project" START { }
create_project -in_memory -part xc7a35tfgg484-2
......@@ -77,12 +80,12 @@ set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir E:/verilogcode/AD_2_UART_V10/fpga_prj.cache/wt [current_project]
set_property parent.project_path E:/verilogcode/AD_2_UART_V10/fpga_prj.xpr [current_project]
set_property webtalk.parent_dir E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.cache/wt [current_project]
set_property parent.project_path E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.xpr [current_project]
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_output_repo e:/verilogcode/AD_2_UART_V10/fpga_prj.cache/ip [current_project]
set_property ip_output_repo e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
OPTRACE "Creating in-memory project" END { }
OPTRACE "Adding files" START { }
......@@ -94,24 +97,25 @@ read_verilog -library xil_defaultlib {
E:/verilogcode/AD_2_UART_V7_test/clkdiv.v
E:/verilogcode/AD_2_UART_V7_test/uart.v
E:/verilogcode/AD_2_UART_V7_test/uarttx.v
E:/verilogcode/AD_2_UART_V10/uisrc/03_ip/uispi7606.v
E:/verilogcode/AD_2_UART_V10/uisrc/01_rtl/ad7606_top.v
E:/verilogcode/AD_2_UART_V10_vol/uisrc/03_ip/uispi7606.v
E:/verilogcode/AD_2_UART_V7_test/volt_cal.v
E:/verilogcode/AD_2_UART_V10_vol/uisrc/01_rtl/ad7606_top.v
}
read_ip -quiet E:/verilogcode/AD_2_UART_V10/fpga_prj.srcs/sources_1/ip/ila_0/ila_0.xci
set_property used_in_synthesis false [get_files -all e:/verilogcode/AD_2_UART_V10/fpga_prj.gen/sources_1/ip/ila_0/ila_v6_2/constraints/ila_impl.xdc]
set_property used_in_implementation false [get_files -all e:/verilogcode/AD_2_UART_V10/fpga_prj.gen/sources_1/ip/ila_0/ila_v6_2/constraints/ila_impl.xdc]
set_property used_in_implementation false [get_files -all e:/verilogcode/AD_2_UART_V10/fpga_prj.gen/sources_1/ip/ila_0/ila_v6_2/constraints/ila.xdc]
set_property used_in_implementation false [get_files -all e:/verilogcode/AD_2_UART_V10/fpga_prj.gen/sources_1/ip/ila_0/ila_0_ooc.xdc]
read_ip -quiet E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.srcs/sources_1/ip/ila_0/ila_0.xci
set_property used_in_synthesis false [get_files -all e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/ila_0/ila_v6_2/constraints/ila_impl.xdc]
set_property used_in_implementation false [get_files -all e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/ila_0/ila_v6_2/constraints/ila_impl.xdc]
set_property used_in_implementation false [get_files -all e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/ila_0/ila_v6_2/constraints/ila.xdc]
set_property used_in_implementation false [get_files -all e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/ila_0/ila_0_ooc.xdc]
read_ip -quiet E:/verilogcode/AD_2_UART_V10/fpga_prj.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
set_property used_in_implementation false [get_files -all e:/verilogcode/AD_2_UART_V10/fpga_prj.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc]
set_property used_in_implementation false [get_files -all e:/verilogcode/AD_2_UART_V10/fpga_prj.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]
set_property used_in_implementation false [get_files -all e:/verilogcode/AD_2_UART_V10/fpga_prj.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc]
read_ip -quiet E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
set_property used_in_implementation false [get_files -all e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc]
set_property used_in_implementation false [get_files -all e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]
set_property used_in_implementation false [get_files -all e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc]
read_ip -quiet E:/verilogcode/AD_2_UART_V10/fpga_prj.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0.xci
set_property used_in_implementation false [get_files -all e:/verilogcode/AD_2_UART_V10/fpga_prj.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc]
set_property used_in_implementation false [get_files -all e:/verilogcode/AD_2_UART_V10/fpga_prj.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc]
set_property used_in_implementation false [get_files -all e:/verilogcode/AD_2_UART_V10/fpga_prj.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_ooc.xdc]
read_ip -quiet E:/verilogcode/AD_2_UART_V10_vol/fpga_prj.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0.xci
set_property used_in_implementation false [get_files -all e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc]
set_property used_in_implementation false [get_files -all e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc]
set_property used_in_implementation false [get_files -all e:/verilogcode/AD_2_UART_V10_vol/fpga_prj.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_ooc.xdc]
OPTRACE "Adding files" END { }
# Mark all dcp files as not used in implementation to prevent them from being
......@@ -122,8 +126,8 @@ OPTRACE "Adding files" END { }
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp
}
read_xdc E:/verilogcode/AD_2_UART_V10/uisrc/04_pin/fpga_pin.xdc
set_property used_in_implementation false [get_files E:/verilogcode/AD_2_UART_V10/uisrc/04_pin/fpga_pin.xdc]
read_xdc E:/verilogcode/AD_2_UART_V10_vol/uisrc/04_pin/fpga_pin.xdc
set_property used_in_implementation false [get_files E:/verilogcode/AD_2_UART_V10_vol/uisrc/04_pin/fpga_pin.xdc]
set_param ips.enableIPCacheLiteLoad 1
close [open __synthesis_is_running__ w]
......
fpga_prj.runs/synth_1/ad7606_top.vds
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fpga_prj.runs/synth_1/gen_run.xml
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fpga_prj.runs/synth_1/runme.log
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fpga_prj.runs/synth_1/runme.sh
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fpga_prj.runs/synth_1/vivado.jou
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fpga_prj.runs/synth_1/vivado.pb
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fpga_prj.srcs/sources_1/ip/ila_0/ila_0.xci
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vivado.jou
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vivado.log
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vivado_16512.backup.jou deleted 100644 → 0
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vivado_24328.backup.jou 0 → 100644
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