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Commit 62c0d596 authored by ywj's avatar ywj
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add udpdk programes , see files in /udpdk/app/dd

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Design.7z deleted 100644 → 0
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FPGA/D-DAQ PL design/D-DAQ PL Design.cache/wt/project.wpc
View file @ 62c0d596
version:1 version:1
57656254616c6b5472616e736d697373696f6e417474656d70746564:68 57656254616c6b5472616e736d697373696f6e417474656d70746564:68
6d6f64655f636f756e7465727c4755494d6f6465:164 6d6f64655f636f756e7465727c4755494d6f6465:165
eof: eof:
FPGA/D-DAQ PL design/vivado.jou
View file @ 62c0d596
...@@ -3,10 +3,10 @@ ...@@ -3,10 +3,10 @@
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Mon Sep 22 12:05:41 2025 # Start of session at: Fri Oct 24 19:57:05 2025
# Process ID: 31204 # Process ID: 51156
# Current directory: G:/HUTP/FPGA/D-DAQ PL design # Current directory: G:/HUTP/FPGA/D-DAQ PL design
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent27240 G:\HUTP\FPGA\D-DAQ PL design\D-DAQ PL design.xpr # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent15632 G:\HUTP\FPGA\D-DAQ PL design\D-DAQ PL design.xpr
# Log file: G:/HUTP/FPGA/D-DAQ PL design/vivado.log # Log file: G:/HUTP/FPGA/D-DAQ PL design/vivado.log
# Journal file: G:/HUTP/FPGA/D-DAQ PL design\vivado.jou # Journal file: G:/HUTP/FPGA/D-DAQ PL design\vivado.jou
# Running On: ye, OS: Windows, CPU Frequency: 2419 MHz, CPU Physical cores: 24, Host memory: 16907 MB # Running On: ye, OS: Windows, CPU Frequency: 2419 MHz, CPU Physical cores: 24, Host memory: 16907 MB
...@@ -14,16 +14,3 @@ ...@@ -14,16 +14,3 @@
start_gui start_gui
open_project {G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.xpr} open_project {G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.xpr}
update_compile_order -fileset sources_1 update_compile_order -fileset sources_1
launch_simulation
source UDP_IP_MAC_PHY_Sim.tcl
current_wave_config {Untitled 1}
add_wave {{/UDP_IP_MAC_PHY_Sim/ad_blob_udp_top_inst/config_request_send}}
current_wave_config {Untitled 1}
add_wave {{/UDP_IP_MAC_PHY_Sim/ad_blob_udp_top_inst/config_request_succed}}
current_wave_config {Untitled 1}
add_wave {{/UDP_IP_MAC_PHY_Sim/ad_blob_udp_top_inst/blob_fifo_udp_transmit_inst/state_arp_reg}}
run all
current_wave_config {Untitled 1}
add_wave {{/UDP_IP_MAC_PHY_Sim/ad_blob_udp_top_inst/blob_fifo_udp_transmit_inst/led_lite_sync}}
run all
close_sim
FPGA/D-DAQ PL design/vivado.log
View file @ 62c0d596
...@@ -3,10 +3,10 @@ ...@@ -3,10 +3,10 @@
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Mon Sep 22 12:05:41 2025 # Start of session at: Fri Oct 24 19:57:05 2025
# Process ID: 31204 # Process ID: 51156
# Current directory: G:/HUTP/FPGA/D-DAQ PL design # Current directory: G:/HUTP/FPGA/D-DAQ PL design
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent27240 G:\HUTP\FPGA\D-DAQ PL design\D-DAQ PL design.xpr # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent15632 G:\HUTP\FPGA\D-DAQ PL design\D-DAQ PL design.xpr
# Log file: G:/HUTP/FPGA/D-DAQ PL design/vivado.log # Log file: G:/HUTP/FPGA/D-DAQ PL design/vivado.log
# Journal file: G:/HUTP/FPGA/D-DAQ PL design\vivado.jou # Journal file: G:/HUTP/FPGA/D-DAQ PL design\vivado.jou
# Running On: ye, OS: Windows, CPU Frequency: 2419 MHz, CPU Physical cores: 24, Host memory: 16907 MB # Running On: ye, OS: Windows, CPU Frequency: 2419 MHz, CPU Physical cores: 24, Host memory: 16907 MB
...@@ -32,530 +32,7 @@ WARNING: [IP_Flow 19-2162] IP 'eth_xcvr_gt_channel' is locked: ...@@ -32,530 +32,7 @@ WARNING: [IP_Flow 19-2162] IP 'eth_xcvr_gt_channel' is locked:
* IP definition 'UltraScale FPGAs Transceivers Wizard (1.7)' for IP 'eth_xcvr_gt_channel' (customized with software release 2020.2) has a different revision in the IP Catalog. * IP definition 'UltraScale FPGAs Transceivers Wizard (1.7)' for IP 'eth_xcvr_gt_channel' (customized with software release 2020.2) has a different revision in the IP Catalog.
WARNING: [IP_Flow 19-2162] IP 'eth_xcvr_gt_full' is locked: WARNING: [IP_Flow 19-2162] IP 'eth_xcvr_gt_full' is locked:
* IP definition 'UltraScale FPGAs Transceivers Wizard (1.7)' for IP 'eth_xcvr_gt_full' (customized with software release 2020.2) has a different revision in the IP Catalog. * IP definition 'UltraScale FPGAs Transceivers Wizard (1.7)' for IP 'eth_xcvr_gt_full' (customized with software release 2020.2) has a different revision in the IP Catalog.
open_project: Time (s): cpu = 00:00:24 ; elapsed = 00:00:17 . Memory (MB): peak = 1731.762 ; gain = 436.680 open_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 1728.641 ; gain = 441.773
update_compile_order -fileset sources_1 update_compile_order -fileset sources_1
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'UDP_IP_MAC_PHY_Sim'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.sim/sim_1/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'D:/Xilinx/Vivado/2023.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'D:/Xilinx/Vivado/2023.2/data/xsim/xsim.ini' copied to run dir:'G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.sim/sim_1/behav/xsim'
INFO: [SIM-utils-20] The project contains locked or custom IPs. The pre-compiled version of these IPs will not be referenced and the sources from these IP libraries will be compiled locally.
INFO: [SIM-utils-54] Inspecting design source files for 'UDP_IP_MAC_PHY_Sim' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj UDP_IP_MAC_PHY_Sim_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.gen/sources_1/ip/ila_2/sim/ila_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ila_2
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.gen/sources_1/ip/ila_0/sim/ila_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ila_0
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_bit_synchronizer
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gte4_drp_arb
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gthe4_delay_powergood
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gtye4_delay_powergood
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gthe3_cpll_cal
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gthe3_cpll_cal_freq_counter
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gthe4_cpll_cal
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gthe4_cpll_cal_rx
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gthe4_cpll_cal_tx
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gthe4_cpll_cal_freq_counter
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_rx
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_tx
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_freq_counter
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gtwiz_buffbypass_rx
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gtwiz_buffbypass_tx
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gtwiz_reset
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gtwiz_userclk_rx
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gtwiz_userclk_tx
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gtwiz_userdata_rx
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gtwiz_userdata_tx
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_reset_synchronizer
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" into library gtwizard_ultrascale_v1_7_9
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.gen/sources_1/ip/eth_xcvr_gt_full/sim/gtwizard_ultrascale_v1_7_gthe4_channel.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gthe4_channel
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.gen/sources_1/ip/eth_xcvr_gt_full/sim/eth_xcvr_gt_full_gthe4_channel_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_xcvr_gt_full_gthe4_channel_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.gen/sources_1/ip/eth_xcvr_gt_full/sim/gtwizard_ultrascale_v1_7_gthe4_common.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtwizard_ultrascale_v1_7_9_gthe4_common
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.gen/sources_1/ip/eth_xcvr_gt_full/sim/eth_xcvr_gt_full_gthe4_common_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_xcvr_gt_full_gthe4_common_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.gen/sources_1/ip/eth_xcvr_gt_full/sim/eth_xcvr_gt_full_gtwizard_gthe4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_xcvr_gt_full_gtwizard_gthe4
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.gen/sources_1/ip/eth_xcvr_gt_full/sim/eth_xcvr_gt_full_gtwizard_top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_xcvr_gt_full_gtwizard_top
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.gen/sources_1/ip/eth_xcvr_gt_full/sim/eth_xcvr_gt_full.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_xcvr_gt_full
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.gen/sources_1/ip/eth_xcvr_gt_channel/sim/eth_xcvr_gt_channel_gthe4_channel_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_xcvr_gt_channel_gthe4_channel_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.gen/sources_1/ip/eth_xcvr_gt_channel/sim/eth_xcvr_gt_channel_gtwizard_gthe4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_xcvr_gt_channel_gtwizard_gthe4
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.gen/sources_1/ip/eth_xcvr_gt_channel/sim/eth_xcvr_gt_channel_gtwizard_top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_xcvr_gt_channel_gtwizard_top
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.gen/sources_1/ip/eth_xcvr_gt_channel/sim/eth_xcvr_gt_channel.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_xcvr_gt_channel
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module clk_wiz_0_clk_wiz
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module clk_wiz_0
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/AD_BLOB_UDP_TOP.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ad_blob_udp_top
WARNING: [VRFC 10-2500] empty parameter declaration is only allowed in SystemVerilog mode [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/AD_BLOB_UDP_TOP.v:21]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'ad_data_valid' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/AD_BLOB_UDP_TOP.v:82]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'ad_blob_ready' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/AD_BLOB_UDP_TOP.v:87]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'config_request_send' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/AD_BLOB_UDP_TOP.v:91]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'config_request_succed' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/AD_BLOB_UDP_TOP.v:92]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'ad_data_slice_axis_tvalid' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/AD_BLOB_UDP_TOP.v:96]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'ad_data_slice_axis_tready' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/AD_BLOB_UDP_TOP.v:97]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'tx_udp_payload_axis_tready' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/AD_BLOB_UDP_TOP.v:154]
WARNING: [VRFC 10-3248] data object 'rx_udp_hdr_ready' is already declared [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/AD_BLOB_UDP_TOP.v:178]
WARNING: [VRFC 10-9364] second declaration of 'rx_udp_hdr_ready' is ignored [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/AD_BLOB_UDP_TOP.v:178]
WARNING: [VRFC 10-3248] data object 'rx_udp_payload_axis_tready' is already declared [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/AD_BLOB_UDP_TOP.v:179]
WARNING: [VRFC 10-9364] second declaration of 'rx_udp_payload_axis_tready' is ignored [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/AD_BLOB_UDP_TOP.v:179]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'udp_tx_rx_delay' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/AD_BLOB_UDP_TOP.v:187]
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/Clock_Reset.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Clock_Reset
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/LTC2324_cmos.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module LTC2324_CMOS
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'ad_sa_count' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/LTC2324_cmos.v:85]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'ad_data_valid' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/LTC2324_cmos.v:402]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'AD_DataA' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/LTC2324_cmos.v:403]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'AD_DataB' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/LTC2324_cmos.v:404]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'AD_DataC' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/LTC2324_cmos.v:405]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'AD_DataD' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/LTC2324_cmos.v:406]
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_ECHO.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module UDP_ECHO
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module UDP_IP_MAC
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'rx_eth_hdr_ready' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:142]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'rx_eth_hdr_valid' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:143]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'rx_eth_dest_mac' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:144]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'rx_eth_src_mac' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:145]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'rx_eth_type' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:146]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'rx_udp_hdr_valid' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:209]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'rx_udp_hdr_ready' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:210]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'rx_udp_payload_axis_tdata' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:231]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'rx_udp_payload_axis_tkeep' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:232]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'rx_udp_payload_axis_tvalid' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:233]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'rx_udp_payload_axis_tready' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:234]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'rx_udp_payload_axis_tlast' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:235]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'rx_udp_payload_axis_tuser' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:236]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'tx_udp_hdr_valid' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:238]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'tx_udp_hdr_ready' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:239]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'tx_udp_ip_source_ip' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:243]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'tx_udp_ip_dest_ip' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:244]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'tx_udp_source_port' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:245]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'tx_udp_dest_port' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:246]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'tx_udp_length' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:247]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'tx_udp_payload_axis_tdata' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:249]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'tx_udp_payload_axis_tkeep' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:250]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'tx_udp_payload_axis_tvalid' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:251]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'tx_udp_payload_axis_tready' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:252]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'tx_udp_payload_axis_tlast' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:253]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'tx_udp_payload_axis_tuser' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:254]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'ip_tx_busy' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:271]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'ip_rx_busy' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:272]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'udp_tx_busy' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:273]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'udp_rx_busy' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:274]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'ip_tx_error_arp_failed' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:275]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'local_mac' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:296]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'local_ip' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:297]
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_NET_PHY.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module UDP_NET_PHY
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_blob_generator.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ad_data_blob_generator
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'data_blob_sa_len' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_blob_generator.v:103]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'data_blob_payload_len' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_blob_generator.v:105]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'data_slice_number' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_blob_generator.v:109]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'data_slice_prev_sa_len' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_blob_generator.v:111]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'data_slice_last_sa_len' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_blob_generator.v:113]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'data_slice_divisible' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_blob_generator.v:119]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'state_ge_reg' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_blob_generator.v:148]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'data_blob_cnt' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_blob_generator.v:161]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'data_slice_cnt' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_blob_generator.v:163]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'data_slice_sa_cnt' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_blob_generator.v:165]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'config_request_send_timer' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_blob_generator.v:167]
WARNING: [VRFC 10-2096] empty statement in sequential block [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_blob_generator.v:379]
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_gen.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ad_data_gen
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'start_ad' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_gen.v:41]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'led_o' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_gen.v:42]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'ad_data_valid' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_gen.v:102]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'ad_data_32ch' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_gen.v:129]
WARNING: [VRFC 10-3380] identifier 'total_sample_cnt' is used before its declaration [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/ad_data_gen.v:75]
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/all_ch_counter.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module all_ch_counter
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/axis/arbiter.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module arbiter
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/arp.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module arp
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/arp_cache.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module arp_cache
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/arp_eth_rx.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module arp_eth_rx
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/arp_eth_tx.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module arp_eth_tx
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/axis/axis_adapter.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_adapter
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/axis/axis_async_fifo.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_async_fifo
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/axis/axis_async_fifo_adapter.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_async_fifo_adapter
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/axis/axis_fifo.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_fifo
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/axis_xgmii_rx_32.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_xgmii_rx_32
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/axis_xgmii_rx_64.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_xgmii_rx_64
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/axis_xgmii_tx_32.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_xgmii_tx_32
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/axis_xgmii_tx_64.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_xgmii_tx_64
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/b64_data_gen.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module b64_data_gen
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'b16_data' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/b64_data_gen.v:183]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'b16_data_valid' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/b64_data_gen.v:184]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'b64_data' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/b64_data_gen.v:341]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'b64_valid' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/b64_data_gen.v:342]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'b64_data_long' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/b64_data_gen.v:444]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'b64_valid_long' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/b64_data_gen.v:445]
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'b64_valid_short' is not allowed [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/b64_data_gen.v:506]
WARNING: [VRFC 10-3380] identifier 'finish' is used before its declaration [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/b64_data_gen.v:92]
WARNING: [VRFC 10-3380] identifier 'finish' is used before its declaration [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/b64_data_gen.v:222]
WARNING: [VRFC 10-3380] identifier 'sample_end' is used before its declaration [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/b64_data_gen.v:269]
WARNING: [VRFC 10-3380] identifier 'sample_end_long' is used before its declaration [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/b64_data_gen.v:270]
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/blob_fifo_udp_transmit.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module blob_fifo_udp_transmit
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/dma_data_gen.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module dma_data_gen
WARNING: [VRFC 10-3380] identifier 'finish' is used before its declaration [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/dma_data_gen.v:91]
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/eth_arb_mux.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_arb_mux
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/eth_axis_rx.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_axis_rx
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/eth_axis_tx.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_axis_tx
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/eth_mac_10g.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_mac_10g
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/eth_mac_10g_fifo.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_mac_10g_fifo
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/eth_phy_10g.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_phy_10g
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/eth_phy_10g_rx.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_phy_10g_rx
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/eth_phy_10g_rx_ber_mon.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_phy_10g_rx_ber_mon
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/eth_phy_10g_rx_frame_sync.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_phy_10g_rx_frame_sync
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/eth_phy_10g_rx_if.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_phy_10g_rx_if
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/eth_phy_10g_rx_watchdog.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_phy_10g_rx_watchdog
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/eth_phy_10g_tx.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_phy_10g_tx
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/eth_phy_10g_tx_if.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_phy_10g_tx_if
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/eth_xcvr_phy_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eth_xcvr_phy_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/ip_64.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ip_64
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/ip_arb_mux.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ip_arb_mux
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/ip_complete_64.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ip_complete_64
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/ip_eth_rx_64.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ip_eth_rx_64
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/ip_eth_tx_64.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ip_eth_tx_64
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/key_10ms.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module key_10ms
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/lfsr.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module lfsr
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/oddr.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module oddr
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module one_ch_counter
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/axis/priority_encoder.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module priority_encoder
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/sync_reset.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module sync_reset
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/sync_signal.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module sync_signal
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/udp_64.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module udp_64
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/udp_checksum_gen_64.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module udp_checksum_gen_64
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/udp_complete_64.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module udp_complete_64
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/udp_ip_rx_64.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module udp_ip_rx_64
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/udp_ip_tx_64.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module udp_ip_tx_64
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/xgmii_baser_dec_64.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module xgmii_baser_dec_64
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/xgmii_baser_enc_64.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module xgmii_baser_enc_64
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sim_1/new/UDP_IP_MAC_PHY_Sim.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module UDP_IP_MAC_PHY_Sim
WARNING: [VRFC 10-3380] identifier 'ad_clkout_tb' is used before its declaration [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sim_1/new/UDP_IP_MAC_PHY_Sim.v:36]
WARNING: [VRFC 10-3380] identifier 'ad_sck_tb' is used before its declaration [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sim_1/new/UDP_IP_MAC_PHY_Sim.v:38]
INFO: [VRFC 10-2263] Analyzing Verilog file "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:17 . Memory (MB): peak = 1820.324 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '17' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L gtwizard_ultrascale_v1_7_9 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot UDP_IP_MAC_PHY_Sim_behav xil_defaultlib.UDP_IP_MAC_PHY_Sim xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2023.2
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
Running: D:/Xilinx/Vivado/2023.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L gtwizard_ultrascale_v1_7_9 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot UDP_IP_MAC_PHY_Sim_behav xil_defaultlib.UDP_IP_MAC_PHY_Sim xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'led_o' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/AD_BLOB_UDP_TOP.v:340]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'data_blob_sa_len' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/AD_BLOB_UDP_TOP.v:524]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 16 for port 'data_slice_number' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/AD_BLOB_UDP_TOP.v:526]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 16 for port 'm_udp_payload_length' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/AD_BLOB_UDP_TOP.v:578]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 's_axis_tid' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/eth_mac_10g_fifo.v:312]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 's_axis_tdest' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/eth_mac_10g_fifo.v:313]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 's_axis_tid' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/eth_mac_10g_fifo.v:364]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 's_axis_tdest' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/eth_mac_10g_fifo.v:365]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 96 for port 's_eth_dest_mac' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/udp_complete_64.v:387]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 96 for port 's_eth_src_mac' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/udp_complete_64.v:388]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 's_ip_version' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/udp_complete_64.v:390]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 's_ip_ihl' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/udp_complete_64.v:391]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 6 for port 's_ip_flags' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/udp_complete_64.v:396]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 26 for port 's_ip_fragment_offset' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/udp_complete_64.v:397]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 16 for port 's_ip_payload_axis_tid' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/udp_complete_64.v:408]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 16 for port 's_ip_payload_axis_tdest' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/udp_complete_64.v:409]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 16 for port 's_eth_payload_axis_tid' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/ip_complete_64.v:293]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 16 for port 's_eth_payload_axis_tdest' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/ip_complete_64.v:294]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 's_axis_tid' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/udp_checksum_gen_64.v:229]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 's_axis_tdest' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/ip/udp_ip_mac_rtl/udp_checksum_gen_64.v:230]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 's_axis_tid' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_ECHO.v:567]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 's_axis_tdest' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_ECHO.v:568]
WARNING: [VRFC 10-3091] actual bit length 6 differs from formal bit length 2 for port 'serdes_tx_hdr' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/eth_xcvr_phy_wrapper.v:282]
WARNING: [VRFC 10-3091] actual bit length 6 differs from formal bit length 2 for port 'serdes_rx_hdr' [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/eth_xcvr_phy_wrapper.v:284]
WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 8 for port 'dmonout_cpl' [/wrk/ci/prod/2023.2/rdi_builds/continuous/2023_10_13_4029153/data/secureip/gthe4_channel/gthe4_channel_002.vp:26135]
WARNING: [VRFC 10-5021] port 'ptp_sample_clk' is not connected on this instance [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_IP_MAC.v:318]
WARNING: [VRFC 10-5021] port 'ptp_sample_clk' is not connected on this instance [G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/UDP_ECHO.v:301]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.srcs/sources_1/new/one_ch_counter.v" Line 1. Module one_ch_counter doesn't have a timescale but at least one module in design has a timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1fs
Compiling module unisims_ver.IBUFDS
Compiling module unisims_ver.IBUFGDS
Compiling module unisims_ver.MMCME4_ADV(CLKFBOUT_MULT_F=10.0,...
Compiling module unisims_ver.MMCME4_BASE(CLKFBOUT_MULT_F=10.0...
Compiling module unisims_ver.BUFG
Compiling module xil_defaultlib.sync_reset(N=4)
Compiling module xil_defaultlib.Clock_Reset
Compiling module unisims_ver.IBUF
Compiling module unisims_ver.MMCME4_ADV(CLKFBOUT_MULT_F=48.0,...
Compiling module xil_defaultlib.clk_wiz_0_clk_wiz
Compiling module xil_defaultlib.clk_wiz_0
Compiling module xil_defaultlib.key_10ms_default
Compiling module unisims_ver.ODDR(DDR_CLK_EDGE="SAME_EDGE",SR...
Compiling module xil_defaultlib.LTC2324_CMOS_default
Compiling module xil_defaultlib.ad_data_gen
Compiling module xil_defaultlib.one_ch_counter
Compiling module xil_defaultlib.all_ch_counter
Compiling module xil_defaultlib.axis_async_fifo(DATA_WIDTH=68,KE...
Compiling module xil_defaultlib.b64_data_gen
Compiling module xil_defaultlib.dma_data_gen
Compiling module xil_defaultlib.ad_data_blob_generator(MAX_PAYLO...
Compiling module xil_defaultlib.sync_signal(N=4)
Compiling module xil_defaultlib.sync_signal(N=5)
Compiling module xil_defaultlib.axis_async_fifo(DATA_WIDTH=64,KE...
Compiling module xil_defaultlib.blob_fifo_udp_transmit(USE_SLICE...
Compiling module xil_defaultlib.lfsr(LFSR_WIDTH=32,LFSR_CONFIG="...
Compiling module xil_defaultlib.axis_xgmii_rx_64(KEEP_WIDTH=8,CT...
Compiling module xil_defaultlib.lfsr(LFSR_WIDTH=32,LFSR_CONFIG="...
Compiling module xil_defaultlib.lfsr(LFSR_WIDTH=32,LFSR_CONFIG="...
Compiling module xil_defaultlib.lfsr(LFSR_WIDTH=32,LFSR_CONFIG="...
Compiling module xil_defaultlib.lfsr(LFSR_WIDTH=32,LFSR_CONFIG="...
Compiling module xil_defaultlib.lfsr(LFSR_WIDTH=32,LFSR_CONFIG="...
Compiling module xil_defaultlib.lfsr(LFSR_WIDTH=32,LFSR_CONFIG="...
Compiling module xil_defaultlib.lfsr(LFSR_WIDTH=32,LFSR_CONFIG="...
Compiling module xil_defaultlib.axis_xgmii_tx_64(KEEP_WIDTH=8,CT...
Compiling module xil_defaultlib.eth_mac_10g(KEEP_WIDTH=8,CTRL_WI...
Compiling module xil_defaultlib.axis_async_fifo(DATA_WIDTH=64,KE...
Compiling module xil_defaultlib.axis_async_fifo_adapter(S_DATA_W...
Compiling module xil_defaultlib.axis_async_fifo(DATA_WIDTH=64,KE...
Compiling module xil_defaultlib.axis_async_fifo_adapter(S_DATA_W...
Compiling module xil_defaultlib.eth_mac_10g_fifo_default
Compiling module xil_defaultlib.eth_axis_rx(DATA_WIDTH=64)
Compiling module xil_defaultlib.eth_axis_tx(DATA_WIDTH=64)
Compiling module xil_defaultlib.priority_encoder(WIDTH=2,LSB_HIG...
Compiling module xil_defaultlib.arbiter(PORTS=2,ARB_BLOCK=1,ARB_...
Compiling module xil_defaultlib.ip_arb_mux(S_COUNT=2,DATA_WIDTH=...
Compiling module xil_defaultlib.eth_arb_mux(S_COUNT=2,DATA_WIDTH...
Compiling module xil_defaultlib.ip_eth_rx_64
Compiling module xil_defaultlib.ip_eth_tx_64
Compiling module xil_defaultlib.ip_64
Compiling module xil_defaultlib.arp_eth_rx(DATA_WIDTH=64,KEEP_EN...
Compiling module xil_defaultlib.arp_eth_tx(DATA_WIDTH=64,KEEP_EN...
Compiling module xil_defaultlib.arp_cache
Compiling module xil_defaultlib.arp(DATA_WIDTH=64,KEEP_ENABLE=1,...
Compiling module xil_defaultlib.ip_complete_64(ARP_REQUEST_RETRY...
Compiling module xil_defaultlib.udp_ip_rx_64
Compiling module xil_defaultlib.axis_fifo(DEPTH=2048,DATA_WIDTH=...
Compiling module xil_defaultlib.udp_checksum_gen_64_default
Compiling module xil_defaultlib.udp_ip_tx_64
Compiling module xil_defaultlib.udp_64_default
Compiling module xil_defaultlib.udp_complete_64
Compiling module xil_defaultlib.UDP_IP_MAC_default
Compiling module xil_defaultlib.axis_fifo(DEPTH=8192,DATA_WIDTH=...
Compiling module xil_defaultlib.UDP_ECHO(LOCAL_MAC=48'b010110100...
Compiling module unisims_ver.IBUFDS_GTE4
Compiling module unisims_ver.GTHE4_COMMON(BIAS_CFG2=16'b01001...
Compiling module xil_defaultlib.gtwizard_ultrascale_v1_7_9_gthe4...
Compiling module xil_defaultlib.eth_xcvr_gt_full_gthe4_common_wr...
Compiling module unisims_ver.GTHE4_CHANNEL(ADAPT_CFG0=16'b010...
Compiling module xil_defaultlib.gtwizard_ultrascale_v1_7_9_gthe4...
Compiling module xil_defaultlib.eth_xcvr_gt_full_gthe4_channel_w...
Compiling module gtwizard_ultrascale_v1_7_9.gtwizard_ultrascale_v1_7_9_gthe4...
Compiling module unisims_ver.BUFG_GT
Compiling module gtwizard_ultrascale_v1_7_9.gtwizard_ultrascale_v1_7_9_gtwiz...
Compiling module gtwizard_ultrascale_v1_7_9.gtwizard_ultrascale_v1_7_9_gtwiz...
Compiling module gtwizard_ultrascale_v1_7_9.gtwizard_ultrascale_v1_7_9_bit_s...
Compiling module gtwizard_ultrascale_v1_7_9.gtwizard_ultrascale_v1_7_9_reset...
Compiling module gtwizard_ultrascale_v1_7_9.gtwizard_ultrascale_v1_7_9_reset...
Compiling module gtwizard_ultrascale_v1_7_9.gtwizard_ultrascale_v1_7_9_gtwiz...
Compiling module gtwizard_ultrascale_v1_7_9.gtwizard_ultrascale_v1_7_9_gtwiz...
Compiling module gtwizard_ultrascale_v1_7_9.gtwizard_ultrascale_v1_7_9_gtwiz...
Compiling module xil_defaultlib.eth_xcvr_gt_full_gtwizard_gthe4(...
Compiling module xil_defaultlib.eth_xcvr_gt_full_gtwizard_top(C_...
Compiling module xil_defaultlib.eth_xcvr_gt_full
Compiling module xil_defaultlib.lfsr(LFSR_WIDTH=58,REVERSE=1,DAT...
Compiling module xil_defaultlib.lfsr(REVERSE=1,DATA_WIDTH=66)
Compiling module xil_defaultlib.eth_phy_10g_rx_frame_sync_defaul...
Compiling module xil_defaultlib.eth_phy_10g_rx_ber_mon(COUNT_125...
Compiling module xil_defaultlib.eth_phy_10g_rx_watchdog(COUNT_12...
Compiling module xil_defaultlib.eth_phy_10g_rx_if(BIT_REVERSE=1,...
Compiling module xil_defaultlib.xgmii_baser_dec_64(CTRL_WIDTH=8)
Compiling module xil_defaultlib.eth_phy_10g_rx(CTRL_WIDTH=8,BIT_...
Compiling module xil_defaultlib.xgmii_baser_enc_64(CTRL_WIDTH=8)
Compiling module xil_defaultlib.eth_phy_10g_tx_if(BIT_REVERSE=1)
Compiling module xil_defaultlib.eth_phy_10g_tx(CTRL_WIDTH=8,BIT_...
Compiling module xil_defaultlib.eth_phy_10g(CTRL_WIDTH=8,BIT_REV...
Compiling module xil_defaultlib.eth_xcvr_phy_wrapper_default
Compiling module xil_defaultlib.eth_xcvr_gt_channel_gthe4_channe...
Compiling module xil_defaultlib.eth_xcvr_gt_channel_gtwizard_gth...
Compiling module xil_defaultlib.eth_xcvr_gt_channel_gtwizard_top...
Compiling module xil_defaultlib.eth_xcvr_gt_channel
Compiling module xil_defaultlib.eth_xcvr_phy_wrapper(HAS_COMMON=...
Compiling module xil_defaultlib.UDP_NET_PHY
Compiling module xil_defaultlib.ila_0
Compiling module xil_defaultlib.ila_2
Compiling module xil_defaultlib.ad_blob_udp_top
Compiling module xil_defaultlib.UDP_IP_MAC_PHY_Sim
Compiling module xil_defaultlib.glbl
Built simulation snapshot UDP_IP_MAC_PHY_Sim_behav
run_program: Time (s): cpu = 00:00:05 ; elapsed = 00:01:54 . Memory (MB): peak = 1821.633 ; gain = 1.309
INFO: [USF-XSim-69] 'elaborate' step finished in '114' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'G:/HUTP/FPGA/D-DAQ PL design/D-DAQ PL design.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "UDP_IP_MAC_PHY_Sim_behav -key {Behavioral:sim_1:Functional:UDP_IP_MAC_PHY_Sim} -tclbatch {UDP_IP_MAC_PHY_Sim.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 fs
source UDP_IP_MAC_PHY_Sim.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# log_wave -r /
WARNING: [Simtcl 6-197] One or more HDL objects could not be logged because of object type or size limitations. To see details please rerun the command with -verbose (-v).
# run 200 us
INFO: [Common 17-41] Interrupt caught. Command should exit soon.
run: Time (s): cpu = 00:02:10 ; elapsed = 00:02:38 . Memory (MB): peak = 1872.480 ; gain = 1.297
INFO: [Common 17-344] 'run' was cancelled
INFO: [Common 17-344] 'source' was cancelled
xsim: Time (s): cpu = 00:02:20 ; elapsed = 00:02:45 . Memory (MB): peak = 1872.480 ; gain = 50.848
INFO: [Common 17-344] 'xsim' was cancelled
INFO: [Vivado 12-5357] 'simulate' step aborted
launch_simulation: Time (s): cpu = 00:02:30 ; elapsed = 00:04:59 . Memory (MB): peak = 1872.480 ; gain = 52.156
INFO: [Common 17-344] 'launch_simulation' was cancelled
current_wave_config {Untitled 1}
Untitled 1
add_wave {{/UDP_IP_MAC_PHY_Sim/ad_blob_udp_top_inst/config_request_send}}
current_wave_config {Untitled 1}
Untitled 1
add_wave {{/UDP_IP_MAC_PHY_Sim/ad_blob_udp_top_inst/config_request_succed}}
current_wave_config {Untitled 1}
Untitled 1
add_wave {{/UDP_IP_MAC_PHY_Sim/ad_blob_udp_top_inst/blob_fifo_udp_transmit_inst/state_arp_reg}}
run all
run: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 2003.238 ; gain = 0.000
current_wave_config {Untitled 1}
Untitled 1
add_wave {{/UDP_IP_MAC_PHY_Sim/ad_blob_udp_top_inst/blob_fifo_udp_transmit_inst/led_lite_sync}}
run all
run: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 2003.238 ; gain = 0.000
close_sim
INFO: xsimkernel Simulation Memory Usage: 139860 KB (Peak: 139860 KB), Simulation CPU Usage: 136468 ms
INFO: [Simtcl 6-16] Simulation closed
exit exit
INFO: [Common 17-206] Exiting Vivado at Mon Sep 22 12:21:18 2025... INFO: [Common 17-206] Exiting Vivado at Fri Oct 24 19:58:04 2025...
udpdk @ b55d19ee
Subproject commit b55d19ee22c67275f734b12045f18f6309492355
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