CRITICAL WARNING: [Common 17-165] Too many positional options when parsing 'clk', please type 'create_clock -help' for usage info. [E:/Verilog/Project/UART_LED_CMD_V2/UART_LED_CMD_V1.srcs/constrs_1/new/fpga_pin.xdc:1]
WARNING: [Constraints 18-619] A clock with name 'clk' already exists, overwriting the previous clock with the same name. [E:/Verilog/Project/UART_LED_CMD_V2/UART_LED_CMD_V1.srcs/constrs_1/new/fpga_pin.xdc:1]
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2023.1/data/ip'.
// HMemoryUtils.trashcanNow. Engine heap size: 1,288 MB. GUI used memory: 86 MB. Current time: 9/23/23, 2:59:21 PM CST
selectTab((HResource) null, (HResource) null, "Messages", 1); // aa
selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at D:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available. ]", 2, true); // u.d - Node
selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at D:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available. , [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at D:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available. ]", 3, false, false, false, false, false, true); // u.d - Double Click
selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Implementation, Route Design, [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.. ]", 7, false); // u.d
selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Implementation, Route Design, [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.. ]", 7, false); // u.d
selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Implementation, Route Design, [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.. ]", 7, false, false, false, false, false, true); // u.d - Double Click
// Elapsed time: 11 seconds
selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Implementation, Route Design, [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.. ]", 7, false); // u.d
selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Implementation, Route Design, [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.. ]", 7, false, false, false, false, false, true); // u.d - Double Click
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Open Implemented Design, Report Timing Summary]", 22, false); // f
// Run Command: PAResourceCommand.PACommandNames_REPORT_TIMING_SUMMARY
selectButton(RDIResource.BaseDialog_OK, "OK"); // a
// HMemoryUtils.trashcanNow. Engine heap size: 2,626 MB. GUI used memory: 186 MB. Current time: 9/23/23, 3:19:56 PM CST
// TclEventType: RUN_STEP_COMPLETED
// Elapsed time: 13 seconds
selectTab((HResource) null, (HResource) null, "Tcl Console", 0); // aa
selectTab((HResource) null, (HResource) null, "Messages", 1); // aa
selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, impl_1, General Messages, [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.. ]", 8, false); // u.d
selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, impl_1, General Messages, [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.. ]", 8, false, false, false, false, false, true); // u.d - Double Click
selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, impl_1, General Messages, [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.. ]", 8, false, false, false, false, true, false); // u.d - Popup Trigger
selectMenu(PAResourceItoN.MsgTreePanel_MESSAGE_SEVERITY, "Message Severity"); // al
// TclEventType: DESIGN_STALE
// TclEventType: RUN_COMPLETED
// TclEventType: RUN_STATUS_CHANGE
// TclEventType: RUN_STEP_COMPLETED
// Elapsed time: 70 seconds
selectRadioButton(PAResourceCommand.PACommandNames_RUN_BITGEN, "Generate Bitstream"); // a
selectButton(RDIResource.BaseDialog_OK, "OK"); // a
// Run Command: PAResourceCommand.PACommandNames_RUN_BITGEN
selectButton(RDIResource.BaseDialog_OK, "OK"); // a
selectButton(RDIResource.BaseDialog_OK, "OK"); // a
dismissDialog("Launch Runs"); // f
// TclEventType: RUN_LAUNCH
// TclEventType: DESIGN_STALE
// TclEventType: RUN_LAUNCH
// TclEventType: RUN_MODIFY
// Tcl Message: launch_runs impl_1 -jobs 16
// Tcl Message: [Sat Sep 23 15:29:36 2023] Launched synth_1... Run output will be captured here: E:/Verilog/Project/UART_LED_CMD_V2/UART_LED_CMD_V1.runs/synth_1/runme.log [Sat Sep 23 15:29:36 2023] Launched impl_1... Run output will be captured here: E:/Verilog/Project/UART_LED_CMD_V2/UART_LED_CMD_V1.runs/impl_1/runme.log
dismissDialog("Starting Design Runs"); // bq
// TclEventType: FILE_SET_CHANGE
// TclEventType: RUN_STATUS_CHANGE
// TclEventType: RUN_COMPLETED
// TclEventType: RUN_STATUS_CHANGE
// TclEventType: RUN_STEP_COMPLETED
// TclEventType: RUN_STATUS_CHANGE
// TclEventType: RUN_STEP_COMPLETED
// TclEventType: DESIGN_STALE
// TclEventType: RUN_COMPLETED
// TclEventType: RUN_STATUS_CHANGE
// TclEventType: RUN_STEP_COMPLETED
// Elapsed time: 90 seconds
selectButton(RDIResource.BaseDialog_OK, "OK"); // a
// Run Command: PAResourceCommand.PACommandNames_REPORTS_WINDOW
dismissDialog("Implementation Completed"); // Q.a
selectTab((HResource) null, (HResource) null, "Messages", 1); // aa
selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Implementation, Route Design, [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.. ]", 7, false); // u.d
selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Implementation, Route Design, [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.. ]", 7, false, false, false, false, false, true); // u.d - Double Click
selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Implementation, Route Design, [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.. ]", 7, false); // u.d
selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Implementation, Route Design, [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.. ]", 7, false, false, false, false, false, true); // u.d - Double Click
selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Project Summary", 0); // o
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, fpga_pin.xdc]", 11, false); // E
// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 2947.160 ; gain = 0.000
// Tcl Message: INFO: [Netlist 29-17] Analyzing 93 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2023.1 INFO: [Project 1-570] Preparing netlist for logic optimization
